|
Buy
|
|
|
Density
|
1.15Gb
|
|
Org
|
32Mx36
|
|
Status
|
S=NOW
|
|
Comment
|
|
|
Interface
|
Common I/O
|
|
Pkg Pins
|
BGA(168)
|
|
Cycle Time Trc
|
6.67, 7.5, 8
|
|
Data Rates Mbps
|
2400, 2133, 1866
|
|
Product Family
|
49RL = RLDRAM 3
|
|
Configuration
|
36320 = 32M x 36
|
|
I/O Type
|
blank = RLDRAM 3
|
IS49RL36320
Features
-
1200 MHz DDR operation (2400 Mb/s/ball
data rate)
-
Organization
-
-
-
64 Meg x 18, and 32 Meg x 36 common I/O (CIO)
16 banks
-
1.2V center-terminated push/pull I/O
-
2.5V VEXT, 1.35V VDD, 1.2V VDDQ (optional 1.35V VDDQ
for 2400 operation only).
Reduced cycle time (tRC (MIN) = 6.67 - 8ns)
-
SDR addressing
-
Programmable READ/WRITE latency (RL/WL) and
burst length
-
Data mask for WRITE commands
-
Fr
DK x#) and output data clocks (QK x, QK x#)
-
On-die DLL generates CK edge-aligned data and
x,
1Gb: x18, x36 RLDRAM 3
Features
Options
-
Clock cycle and
tRC timing
-
- 0.83ns and tRC (MIN) = 6.67ns (RL3-2400) for -083F
- 0.83ns and tRC (MIN) = 7.5ns (RL3-2400) for -083E
- 0.93ns and tRC (MIN) = 7.5ns (RL3-2133) for -093F
- 0.93ns and tRC (MIN) = 8ns (RL3-2133) for -093E
- 1.07ns and tRC (MIN) = 8ns (RL3-1866) for -107E
-
64ms refresh (128K refresh per 64ms)
-
168-ball FBGA package
-
40 Ω or 60 Ω matched impedance outputs
-
Integrated on-die termination (ODT)
-
Single or multibank writes
-
Extended operating range (200
-
READ training register
-
Multiplexed and non-multiplexed addressing capa-
bilities
-
Mirror function
-
Output driver and ODT calibration
-
Post Package Repar - 1 row per half bank