IS49RL18320-125EBLI-TR
Features
-
1066 MHz DDR operation (2133 Mb/s/ball data
-
76.8 Gb/s peak bandwidth (x36 at 1066 MHz clock
rate)
frequency)
-
Organization
-
- 32 Meg x 18, and 16 Meg x 36 common I/O (CIO)
- 16 banks
-
1.2V center-terminated push/pull I/O
-
2.5V V EXT , 1.35V V DD , 1.2V V DDQ I/O
-
Reduced cycle time ( tRC (MIN) = 8 - 12ns)
-
SDR addressing
-
Programmable READ/WRITE latency (RL/WL) and
burst length
-
Data mask for WRITE commands
-
Fr
DK x#) and output data clocks (QK x, QK x#)
-
On-die DLL generates CK edge-aligned data and
x,
Ω or 60 Ω matched impedance outputs
-
64ms refresh (128K refresh per 64ms)
-
168-ball FBGA package
-
Integrated on-die termination (ODT)
-
Single or multibank writes
-
Extended operating range (200
-
READ training register
-
Multiplexed and non-multiplexed addressing capa-
bilities
-
Mirror function
-
Output driver and ODT calibration
-
JTAG interface (IEEE 1149.1-2001)
Options
-
Clock cycle and
tRC timing
-
- 0.93ns and tRC (MIN) = 8ns
(RL3-2133)
(RL3-2133)
(RL3-1866)
(RL3-1866)
(RL3-1600)
(RL3-1600)
- 0.93ns and tRC (MIN) = 10ns
- 1.07ns and tRC (MIN) = 8ns
- 1.07ns and tRC (MIN) = 10ns
- 1.25ns and tRC (MIN) = 8ns
- 1.25ns and tRC (MIN) = 10ns
- 1.25ns and tRC (MIN) = 12ns
(RL3-1600)
Con(cid:31)guration
-32 Meg x 18
- 16 Meg x 36
Operating Temperature
- Commercial (TC = 0° to +95°C)
- Industrial (TC =
- 40°C to +95°C)
Package
- 168-ball FBGA
- 168-ball FBGA (Pb-free)
-
Revision