| Density | 288M |
|---|---|
| Org | 32Mx9 |
| Status | Prod |
| Comment | |
| Interface | Common I/O |
| Pkg Pins | BGA(144) |
| Product Family | 49NL = RLDRAM 2 |
| Configuration | 93200 = 32M x 9 |
| Package Code | WB = WB |
| Speed Grade | 33 = tCK = 3.3ns; tRC = 20ns |
| ROHS Version | L = Lead-free (RoHS compliant) |
| Package Number | WB = 144 - ball WBGA (RLDRAM 2) |
| I/O Type | C = Common I/O |
| Temperature Range | = Commercial (0C to 70°C) |
| Outpack | Tape on Reel |
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
| Description | Stock Qty | Available Qty | Description | Stock Qty | Available Qty |
|---|---|---|---|---|---|
| IS49NLC93200-33WBL | 100,000 | IS49NLC93200-25WBLI | 100,000 | ||
| IS49NLC93200 | IS49NLC93200-25WBLI-TR | ||||
| IS49NLC93200-25EWBL | 100,000 | IS49NLC93200-33WBLI | 18 | ||
| IS49NLC93200-25EWBL-TR | IS49NLC93200-33WBLI-TR | ||||
| IS49NLC93200-25EWBLI | 100,000 | IS49NLC93200-5WBL | |||
| IS49NLC93200-25EWBLI-TR | IS49NLC93200-5WBL-TR | ||||
| IS49NLC93200-25WBL | 100,000 | IS49NLC93200-5WBLI | |||
| IS49NLC93200-25WBL-TR | IS49NLC93200-5WBLI-TR |