Density | 288M |
---|---|
Org | 8Mx36 |
Status | Prod |
Comment | |
Interface | Common I/O |
Pkg Pins | BGA(144) |
Product Family | 49NL = RLDRAM 2 |
Configuration | 36800 = 8M x 36 |
Package Code | B = B |
Speed Grade | 5 = tCK = 5ns; tRC = 20ns |
ROHS Version | = SnPb |
Package Number | B = 144-ball FBGA (RLDRAM 2) |
I/O Type | C = Common I/O |
Temperature Range | = Commercial (0C to 70°C) |
Outpack | Tape on Reel |
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.
Description | Stock Qty | Available Qty | Description | Stock Qty | Available Qty |
---|---|---|---|---|---|
IS49NLC36800-5B | IS49NLC36800-33WBL-TR | ||||
IS49NLC36800 | IS49NLC36800-33WBLI | 2 | |||
IS49NLC36800-25EWBL | 248 | IS49NLC36800-33WBLI-TR | |||
IS49NLC36800-25EWBL-TR | IS49NLC36800-5BL | ||||
IS49NLC36800-25EWBLI | 10 | IS49NLC36800-5BL-TR | |||
IS49NLC36800-25EWBLI-TR | IS49NLC36800-5WBL | ||||
IS49NLC36800-25WBL | 1,961 | IS49NLC36800-5WBL-TR | |||
IS49NLC36800-25WBL-TR | IS49NLC36800-5WBLI | ||||
IS49NLC36800-25WBLI | 4 | IS49NLC36800-5WBLI-TR | |||
IS49NLC36800-25WBLI-TR | IS49NLC36800-TR | ||||
IS49NLC36800-33WBL | 100,000 |