| Density | 576M |
|---|---|
| Org | 32Mx18 |
| Status | Prod |
| Comment | |
| Interface | Common I/O |
| Pkg Pins | BGA(144) |
| Product Family | 49NL = RLDRAM 2 |
| Configuration | 18320 = 32M x 18 |
| Package Code | B = B |
| Speed Grade | 5 = tCK = 5ns; tRC = 20ns |
| ROHS Version | = SnPb |
| Package Number | B = 144-ball FBGA (RLDRAM 2) |
| I/O Type | C = Common I/O |
| Temperature Range | = Commercial (0C to 70°C) |
| Outpack | Tape on Reel |
Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.