1. ISSI
  2. DRAM
  3. RLDRAM® Memory
  4. RLDRAM® 2 Memory
  5. 288M 32Mx9
  6. BGA(144)
  7. IS49NLC18160-25EB

  IS49NLC18160-25EB

Datasheet
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Density 288M
Org 32Mx9
Pkg(Pins) BGA(144)
Speed tCK = 2.5ns; tRC = 15ns
Solder SnPb
Status Prod
Interface Common I/O
Temp.Range Commercial Grade (0C to +70°C)
Product Family 49NL = RLDRAM 2
Configuration 18160 = 16M x 18
Package Code B = B
Speed Grade 25E = tCK = 2.5ns; tRC = 15ns
ROHS Version = SnPb
Package Number B = 144-ball FBGA (RLDRAM 2)
I/O Type C = Common I/O
Temperature Range = Commercial (0C to 70°C)
Datasheet
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IS49NLC18160-25EB Features

  • 400MHz DDR operation (800Mb/s/pin data rate) 28.8Gb/s peak bandwidth (x36 at 400 MHz clock frequency)
  • Differential input clocks (CK, CK#)
  • Differential input data clocks (DKx, DKx#)
  • On-die DLL generates CK edge-aligned data and
  • Reduced cycle time (15ns at 400MHz)
  • 32ms refresh (8K refresh for each bank; 64K refresh command must be issued in total each 32ms) 8 internal banks
  • Non-multiplexed addresses (address multiplexing
  • option available) SRAM-type interface Programmable READ latency (RL), row cycle time, and burst sequence length
  • Balanced READ and WRITE latencies in order to optimize data bus utilization
  • Data mask signals (DM) to mask signal of WRITE data; DM is sampled on both edges of DK. output data clock signals
  • Data valid signal (QVLD)
  • HSTL I/O (1.5V or 1.8V nominal)
  • On-die termination (ODT) RTT
  • Operating temperature: 25-60Ω matched impedance outputs 2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O IEEE 1149.1 compliant JTAG boundary scan Commercial (TC = 0° to +95°C; TA = 0°C to +70°C), Industrial (TC = -40°C to +95°C; TA = -40°C to +85°C) OPTIONS Package:

Overview

Address inputs: Defines the row and column addresses for READ and WRITE operations. During a MODE REGISTER SET, the address inputs define the register settings. They are sampled at the rising edge of CK. Bank address inputs: Selects to which internal bank a command is being applied to. Input clock: CK and CK# are differential input clocks. Addresses and commands are latched on the rising edge of CK. CK# is ideally 180 degrees out of phase with CK.