|
Density
|
288M
|
|
Org
|
16Mx18
|
|
Status
|
Prod
|
|
Comment
|
|
|
Interface
|
Common I/O
|
|
Pkg Pins
|
BGA(144)
|
|
Product Family
|
49NL = RLDRAM 2
|
|
Configuration
|
18160 = 16M x 18
|
|
I/O Type
|
C = Common I/O
|
IS49NLC18160
Features
-
400MHz DDR operation (800Mb/s/pin data rate)
28.8Gb/s peak bandwidth (x36 at 400 MHz clock
frequency)
-
Reduced cycle time (15ns at 400MHz)
-
32ms refresh (8K refresh for each bank; 64K refresh
command must be issued in total each 32ms)
8 internal banks
-
Non-multiplexed addresses (address multiplexing
-
option available)
SRAM-type interface
Programmable READ latency (RL), row cycle time,
and burst sequence length
-
Balanced READ and WRITE latencies in order to
optimize data bus utilization
-
Data mask signals (DM) to mask signal of WRITE
data; DM is sampled on both edges of DK.
-
Differential input clocks (CK, CK#)
-
Differential input data clocks (DKx, DKx#)
-
On-die DLL generates CK edge-aligned data and
output data clock signals
-
Data valid signal (QVLD)
-
HSTL I/O (1.5V or 1.8V nominal)
-
On-die termination (ODT) RTT
-
Operating temperature:
25-60Ω matched impedance outputs
2.5V VEXT, 1.8V VDD, 1.5V or 1.8V VDDQ I/O
IEEE 1149.1 compliant JTAG boundary scan
Commercial
(TC = 0° to +95°C; TA = 0°C to +70°C),
Industrial
(TC = -40°C to +95°C; TA = -40°C to +85°C)
-
OPTIONS
Package: