| Density | 72M |
|---|---|
| Org | 4Mx18 |
| Burst | 4 |
| Status | Prod |
| Speed Mhz | 450, 500, 550, 567 |
| Comments Previous Revision | 2.5 Cycle Read Latency, IS61QDPB24M18A/A1/A2 |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 4M18 = 4M x18 |
| Package Code | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS Version | = Leaded |
| Burst Type | B4 = Burst 4 |
| Die Rev | C = C |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | 1 = ODT Option 1 If ODT = HIGH or floating, a high range termination resistance is selected. If ODT = LOW, a low range termination resistance is selected. |
| Product Type | QDP = QUADP |
| Temperature Range | blank = Commercial (0°C to 70°C) |
| Speed | 500 = 500MHz |
| Outpack | Tape on Reel |
The 72Mb IS61QDPB42M36C/C1/C2 and IS61QDPB44M18 C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: