Density | 18M |
---|---|
Org | 1Mx18 |
Burst | 4 |
Status | Prod |
Speed Mhz | 450, 500, 550, 567 |
Comments Previous Revision | 2.5 Cycle Read Latency |
Product Family | 61 = QUAD/P DDR-2/P |
Configuration | 1M18 = 1M x18 |
Package Code | B4 = 165 ball BGA (13 x 15 mm) |
ROHS Version | L = Lead-free |
Burst Type | B4 = Burst 4 |
Die Rev | C = C |
Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
ODT Option | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
Product Type | QDP = QUADP |
Temperature Range | blank = Commercial (0°C to 70°C) |
Speed | 550 = 550MHz |
Outpack | Tape on Reel |
The 18Mb IS61QDPB451236C/C1/C2 and IS61QDPB41M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: