| Density | 72M |
|---|---|
| Org | 2Mx36 |
| Burst | 2 |
| Status | Prod |
| Speed Mhz | 300, 333, 400, 450 |
| Comments Previous Revision | 2.5 Cycle Read Latency |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 2M36 = 2M x36 |
| Package Code | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS Version | L = Lead-free |
| Burst Type | B2 = Burst 2 |
| Die Rev | C = C |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | 1 = ODT Option 1 If ODT = HIGH or floating, a high range termination resistance is selected. If ODT = LOW, a low range termination resistance is selected. |
| Product Type | QDP = QUADP |
| Temperature Range | I = Industrial (-40°C to +85°C) |
| Speed | 400 = 400MHz |
| Outpack | Tape on Reel |
The IS61QDPB22M36C/C1/C2 and IS61QDPB24M18C/C1/ -C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the description of the basic operations of these.