IS61QDPB21M18C2-500M3L-TR

Density 18M
Org 1Mx18
Burst 2
Status Prod
Speed Mhz 333, 400, 450, 500
Comments Previous Revision 2.5 Cycle Read Latency
Configuration 1M18 = 1M x18
ROHS Version L = Lead-free
Burst Type B2 = Burst 2
Die Rev C = C
Read Latency (RL) blank = 1.5 clock cycles or 2.5 clock cycles
Product Type QDP = QUADP
ODT Option 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled
Temperature Range blank = Commercial (0°C to 70°C)
Speed 500 = 500MHz
Product Family 61 = QUAD/P DDR-2/P
Package Code M3 = 165-ball BGA (15 x 17 mm)
Outpack Tape on Reel

IS61QDPB21M18C2-500M3L-TR Features

  • 512Kx36 and 1Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with EARLY write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.5 Cycle read latency. Fixed 2-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data valid pin (QVLD).
  • HSTL input and output interface.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs.
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1 functions.
  • Byte Write capability.
  • Fine ball grid array (FBGA) package option: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user- supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • Read address
  • Read enable
  • Write enable
  • Data-in for early writes The following are registered on the rising edge of the K# clock:
  • Write address
  • Byte writes

Overview

The are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the for a description of the basic.

 

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