1. ISSI
  2. SRAM
  3. QUAD/QUADP and DDR-II/DDR-IIP
  4. QUADP
  5. 36M 1Mx36
  6. 165 ball BGA (13 x 15 mm)
  7. IS61QDP2B41M36A-450B4-TR

  IS61QDP2B41M36A-450B4-TR

Datasheet
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Density 36M
Org 1Mx36
Burst 4
Status Prod
Speed Mhz 300, 333, 400, 450
Comments Previous Revision 2.0 Cycle Read Latency
Product Family 61 = QUAD/P DDR-2/P
Configuration 1M36 = 1M x36
Package Code B4 = 165 ball BGA (13 x 15 mm)
ROHS Version = Leaded
Burst Type B4 = Burst 4
Die Rev A = A
Read Latency (RL) 2 = 2.0 clock cycles
ODT Option blank = No ODT
Product Type QDP = QUADP
Temperature Range blank = Commercial (0°C to 70°C)
Speed 450 = 450MHz
Outpack Tape on Reel
Datasheet
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IS61QDP2B41M36A-450B4-TR Features

  • 1Mx36 and 2Mx18 configuration available.
  • On-chip Delay-Locked Loop (DLL) for wide data valid window.
  • Separate independent read and write ports with concurrent read and write operations.
  • Synchronous pipeline read with late write operation.
  • Double Data Rate (DDR) interface for read and write input ports. 2.0 cycle read latency. Fixed 4-bit burst for read and write operations.
  • Clock stop support.
  • Two input clocks (K and K#) for address and control registering at rising edges only. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data.
  • Data Valid Pin (QVLD).
  • HSTL input and output interface. functions.
  • Byte write capability.
  • Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
  • Programmable impedance output drivers via 5x user-supplied precision resistor.
  • ODT (On Die Termination) feature is supported
  • Read/write address
  • Read enable
  • Write enable
  • Byte writes for burst addresses 1 and 3
  • Data-in for burst addresses 1 and 3 Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. Two full clock cycles are required to complete a write operation. During the burst read operation, the data-outs from the first and third bursts are updated from output registers of the third and fourth rising edges of the K clock (starting 2.0 cycles later after read command). The data-outs from the second and fourth bursts are updated with the third and fourth rising edges of the K# clock where the read command receives at the first rising edge of K. Two full clock cycles are required to complete a read operation. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces.
  • Registered addresses, write and read controls, byte writes, data in, and data outputs. The following are registered on the rising edge of the K# clock:
  • Full data coherency.
  • Boundary scan using limited set of JTAG 1149.1
  • Byte writes for burst addresses 2 and 4

Overview

The 36Mb IS61QDP2B41M36A/A1/A2 and IS61QDP2B42M18A/A1/A2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS61QDP2B41M36A-300B4 IS61QDP2B41M36A1-300M3
IS61QDP2B41M36A-300B4-TR IS61QDP2B41M36A1-300M3-TR
IS61QDP2B41M36A-300B4I IS61QDP2B41M36A1-300M3I
IS61QDP2B41M36A-300B4I-TR IS61QDP2B41M36A1-300M3I-TR
IS61QDP2B41M36A-300B4L IS61QDP2B41M36A1-300M3L
IS61QDP2B41M36A-300B4L-TR IS61QDP2B41M36A1-300M3L-TR
IS61QDP2B41M36A-300B4LI IS61QDP2B41M36A1-300M3LI
IS61QDP2B41M36A-300B4LI-TR IS61QDP2B41M36A1-300M3LI-TR
IS61QDP2B41M36A-300M3 IS61QDP2B41M36A1-333B4
IS61QDP2B41M36A-300M3-TR IS61QDP2B41M36A2-300B4
IS61QDP2B41M36A-300M3I IS61QDP2B41M36A2-300B4-TR
IS61QDP2B41M36A-300M3I-TR IS61QDP2B41M36A2-300B4I
IS61QDP2B41M36A-300M3L 10,000 IS61QDP2B41M36A2-300B4I-TR
IS61QDP2B41M36A-300M3L-TR IS61QDP2B41M36A2-300B4L
IS61QDP2B41M36A-300M3LI 10,000 IS61QDP2B41M36A2-300B4L-TR
IS61QDP2B41M36A-300M3LI-TR IS61QDP2B41M36A2-300B4LI
IS61QDP2B41M36A-333B4 IS61QDP2B41M36A2-300B4LI-TR
IS61QDP2B41M36A-333B4-TR IS61QDP2B41M36A2-300M3
IS61QDP2B41M36A1-300B4 IS61QDP2B41M36A2-300M3-TR
IS61QDP2B41M36A1-300B4-TR IS61QDP2B41M36A2-300M3I
IS61QDP2B41M36A1-300B4I IS61QDP2B41M36A2-300M3I-TR
IS61QDP2B41M36A1-300B4I-TR IS61QDP2B41M36A2-300M3L
IS61QDP2B41M36A1-300B4L IS61QDP2B41M36A2-300M3L-TR
IS61QDP2B41M36A1-300B4L-TR IS61QDP2B41M36A2-300M3LI
IS61QDP2B41M36A1-300B4LI IS61QDP2B41M36A2-300M3LI-TR
IS61QDP2B41M36A1-300B4LI-TR
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