| Density | 72M |
|---|---|
| Org | 2Mx36 |
| Burst | 2 |
| Status | Prod |
| Speed Mhz | 300, 333, 400, 450 |
| Comments Previous Revision | 2.0 Cycle Read Latency |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 2M36 = 2M x36 |
| Package Code | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS Version | L = Lead-free |
| Burst Type | B2 = Burst 2 |
| Die Rev | C = C |
| Read Latency (RL) | 2 = 2.0 clock cycles |
| ODT Option | blank = No ODT |
| Product Type | QDP = QUADP |
| Temperature Range | blank = Commercial (0°C to 70°C) |
| Speed | 450 = 450MHz |
The IS61QDP2B22M36C/C1/C2 and IS61QDP2B24M18 C/C1/C2 are 72Mb synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUADP (Burst of 2) SRAMs. The input address bus operates at double data rate. Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered half a cycle earlier than the write address. The first data-in burst is clocked at the same time as the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the K# clock (starting two and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the K clock. The K and K# clocks are used to time the data-outs. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interface.