IS61QDB451236A

Density	18M
Org	512Kx36
Burst	4
Status	Prod
Speed Mhz	250, 300, 333, 400
Comments Previous Revision

Density

18M

Org

512Kx36

Burst

Status

Prod

Speed Mhz

250, 300, 333, 400

Comments Previous Revision

IS61QDB451236A Features

512Kx36 and 1Mx18 configuration available.
On-chip Delay-Locked loop (DLL) for wide data valid window.
Separate independent read and write ports with concurrent read and write operations.
Synchronous pipeline read with late write operation.
Double Data Rate (DDR) interface for read and write input ports. 1.5 cycle read latency. Fixed 4-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
Read/write address
Read enable
Write enable
Byte writes for burst addresses 1 and 3
Data-in for burst addresses 1 and 3 The following are registered on the rising edge of the K# clock:
Registered addresses, write and read controls, byte
Byte writes for burst addresses 2 and 4 writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array
Programmable impedance output drivers via 5x user-supplied precision resistor.

Overview

The 18Mb IS61QDB451236A and IS61QDB41M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock:

Description

Stock Qty

Available Qty

Description

Stock Qty

Available Qty

IS61QDB451236A-250B4

IS61QDB451236A-300M3I

IS61QDB451236A-250B4-TR

IS61QDB451236A-300M3I-TR

IS61QDB451236A-250B4I

IS61QDB451236A-300M3L