| Density | 72M |
|---|---|
| Org | 2Mx36 |
| Burst | 4 |
| Status | Prod |
| Speed Mhz | 250, 300, 333, 400 |
| Comments Previous Revision | IS61QDB42M36, Application Note |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 2M36 = 2M x36 |
| Package Code | B4 = 165 ball BGA (13 x 15 mm) |
| ROHS Version | = Leaded |
| Burst Type | B4 = Burst 4 |
| Die Rev | A = A |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | blank = No ODT |
| Product Type | QD = QUAD |
| Temperature Range | I = Industrial (-40°C to +85°C) |
| Speed | 250 = 250MHz |
| Outpack | Tape on Reel |
The 72Mb IS61QDB42M36A and IS61QDB44M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these QUAD (Burst of 4) SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: