IS61QDB24M18C

Density	72M
Org	4Mx18
Burst	2
Status	Prod
Speed Mhz	250, 300, 333, 400
Comments Previous Revision	IS61QDB24M18A

Density

72M

Org

4Mx18

Burst

Status

Prod

Speed Mhz

250, 300, 333, 400

Comments Previous Revision

IS61QDB24M18A

IS61QDB24M18C Features

2Mx36 and 4Mx18 configuration available.
Separate independent read and write ports with concurrent read and write operations.
Max. 400 MHz clock for high bandwidth
Synchronous pipeline read with EARLY write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two output clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5, 1.8V VDDQ, used with 0.75, 0.9V VREF.
HSTL input and output interface.
Full data coherency.
On-chip Delay-Locked loop (DLL) for wide data valid window.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array

Overview

The chronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initi- ates the read/write operation, and all internal operations are self-timed. Refer to the description of the basic operations of these.

Description

Stock Qty

Available Qty

Description

Stock Qty

Available Qty

IS61QDB24M18C-250B4

IS61QDB24M18C-300M3I

IS61QDB24M18C-250B4-TR

IS61QDB24M18C-300M3I-TR

IS61QDB24M18C-250B4I

IS61QDB24M18C-300M3L