| Density | 72M |
|---|---|
| Org | 4Mx18 |
| Burst | 2 |
| Status | Prod |
| Speed Mhz | 250, 300, 333, 400 |
| Comments Previous Revision | IS61QDB24M18A |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 4M18 = 4M x18 |
| Package Code | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS Version | L = Lead-free |
| Burst Type | B2 = Burst 2 |
| Die Rev | C = C |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | blank = No ODT |
| Product Type | QD = QUAD |
| Temperature Range | blank = Commercial (0°C to 70°C) |
| Speed | 400 = 400MHz |
The chronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have separate I/Os, eliminating the need for high-speed bus turnaround. The rising edge of K clock initi- ates the read/write operation, and all internal operations are self-timed. Refer to the description of the basic operations of these.