Density | 18M |
---|---|
Org | 512Kx36 |
Burst | 2 |
Status | Prod |
Speed Mhz | 250, 300, 333, 400 |
Comments Previous Revision | Separate I/O |
The 18Mb IS61DDSB251236C and IS61DDSB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a separate I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) SIO SRAMs.