| Density | 18M |
|---|---|
| Org | 512Kx36 |
| Burst | 4 |
| Status | Prod |
| Speed Mhz | 450, 500, 550, 567 |
| Comments Previous Revision | 2.5 Cycle Read |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 51236 = 512K x36 |
| Package Code | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS Version | = Leaded |
| Burst Type | B4 = Burst 4 |
| Die Rev | C = C |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
| Product Type | DDP = DDR-IIP, Common I/O |
| Temperature Range | I = Industrial (-40°C to +85°C) |
| Speed | 500 = 500MHz |
The 18Mb IS61DDPB451236C/C1/C2 and IS61DDPB41M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self- timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 4) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: