| Density | 36M |
|---|---|
| Org | 1Mx36 |
| Burst | 4 |
| Status | Prod |
| Speed Mhz | 400, 450, 500, 550 |
| Comments Previous Revision | 2.5 Cycle Read |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 1M36 = 1M x36 |
| Package Code | M3 = 165-ball BGA (15 x 17 mm) |
| ROHS Version | = Leaded |
| Burst Type | B4 = Burst 4 |
| Die Rev | B = B |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | 1 = ODT Option 1 If ODT = HIGH or floating, a high range termination resistance is selected. If ODT = LOW, a low range termination resistance is selected. |
| Product Type | DDP = DDR-IIP, Common I/O |
| Temperature Range | blank = Commercial (0°C to 70°C) |
| Speed | 450 = 450MHz |
| Outpack | Tape on Reel |
The 36Mb IS61DDPB41M36B/B1/B2 and IS61DDPB42M18B/B1/B2 are synchronous, high- performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 4) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: