Density | 36M |
---|---|
Org | 2Mx18 |
Burst | 2 |
Status | Prod |
Speed Mhz | 450, 500, 550, 567 |
Comments Previous Revision | 2.5 Cycle Read |
Configuration | 2M18 = 2M x18 |
Speed | 550 = 550MHz |
Product Family | 61 = QUAD/P DDR-2/P |
Package Code | B4 = 165 ball BGA (13 x 15 mm) |
ROHS Version | L = Lead-free |
Burst Type | B2 = Burst 2 |
Die Rev | C = C |
Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
Product Type | DDP = DDR-IIP, Common I/O |
ODT Option | 2 = ODT Option 2 If ODT = HIGH, a high range termination resistance is selected. If ODT = LOW or floating, ODT is disabled |
Temperature Range | blank = Commercial (0°C to 70°C) |
The 36Mb IS61DDPB21M36C/C1/C2 and IS61DDPB22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self- timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: