Density | 36M |
---|---|
Org | 1Mx36 |
Burst | 2 |
Status | Prod |
Speed Mhz | 300, 333, 400, 450 |
Comments Previous Revision | 2.0 Cycle Read |
Product Family | 61 = QUAD/P DDR-2/P |
Configuration | 1M36 = 1M x36 |
Package Code | B4 = 165 ball BGA (13 x 15 mm) |
ROHS Version | = Leaded |
Burst Type | B2 = Burst 2 |
Die Rev | C = C |
Read Latency (RL) | 2 = 2.0 clock cycles |
ODT Option | blank = No ODT |
Product Type | DDP = DDR-IIP, Common I/O |
Temperature Range | I = Industrial (-40°C to +85°C) |
Speed | 400 = 400MHz |
The 36Mb IS61DDP2B21M36C/C1/C2 and IS61DDP2B22M18C/C1/C2 are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self- timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-IIP (Burst of 2) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: