Density | 18M |
---|---|
Org | 1Mx18 |
Burst | 4 |
Status | Prod |
Speed Mhz | 250, 300, 333 |
Comments Previous Revision |
The 18Mb IS61DDB451236A and IS61DDB41M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 4) CIO SRAMs. Read and write addresses are registered on alternating rising edges of the K clock. Reads and writes are performed in double data rate. The following are registered internally on the rising edge of the K clock: