IS61DDB251236C

Density	18M
Org	512Kx36
Burst	2
Status	Prod
Speed Mhz	250, 300, 333, 400
Comments Previous Revision

Density

18M

Org

512Kx36

Burst

Status

Prod

Speed Mhz

250, 300, 333, 400

Comments Previous Revision

IS61DDB251236C Features

Read/write address
Read enable
Write enable
Byte writes for first burst address
Data-in for first burst address The following are registered on the rising edge of the K# clock.
Byte writes for second burst address
Data-in for second burst address Byte writes can change with the corresponding data-in to enable or disable writes on a per-byte basis. An internal write buffer enables the data-ins to be registered one cycle after the write address. The first data-in burst is clocked one cycle later than the write command signal, and the second burst is timed to the following rising edge of the K# clock. During the burst read operation, the data-outs from the first bursts are updated from output registers of the second rising edge of the C# clock (starting one and half cycles later after read command). The data-outs from the second bursts are updated with the third rising edge of the C clock. The K and K# clocks are used to time the data-outs whenever the C and C# clocks are tied high. The device is operated with a single +1.8V power supply and is compatible with HSTL I/O interfaces. IS61DDB21M18C IS61DDB251236C
512Kx36 and 1Mx18 configuration available.
On-chip delay-locked loop (DLL) for wide data valid window.
Common I/O read and write ports.
Synchronous pipeline read with self-timed late write operation.
Double Data Rate (DDR) interface for read and write input ports.
Fixed 2-bit burst for read and write operations.
Clock stop support.
Two input clocks (K and K#) for address and control registering at rising edges only. Two input clocks (C and C#) for data output control. Two echo clocks (CQ and CQ#) that are delivered simultaneously with data. +1.8V core power supply and 1.5V to 1.8V VDDQ, used with 0.75V to 0.9V VREF.
HSTL input and output interface.
Registered addresses, write and read controls, byte writes, data in, and data outputs.
Full data coherency.
Boundary scan using limited set of JTAG 1149.1 functions.
Byte write capability.
Fine ball grid array (FBGA) package: 13mmx15mm and 15mmx17mm body size 165-ball (11 x 15) array

Overview

The 18Mb IS61DDB251236C and IS61DDB21M18C are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs.

Description

Stock Qty

Available Qty

Description

Stock Qty

Available Qty

IS61DDB251236C-250B4

IS61DDB251236C-300M3I

IS61DDB251236C-250B4-TR

IS61DDB251236C-300M3I-TR

IS61DDB251236C-250B4I

IS61DDB251236C-300M3L