Density | 36M |
---|---|
Org | 2Mx18 |
Burst | 2 |
Status | Prod |
Speed Mhz | 250, 300, 333 |
Comments Previous Revision | IS61DDB22M18 |
The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs.