| Density | 36M |
|---|---|
| Org | 1Mx36 |
| Burst | 2 |
| Status | Prod |
| Speed Mhz | 250, 300, 333 |
| Comments Previous Revision | IS61DDB21M36 |
| Product Family | 61 = QUAD/P DDR-2/P |
| Configuration | 1M36 = 1M x36 |
| Package Code | B4 = 165 ball BGA (13 x 15 mm) |
| ROHS Version | = Leaded |
| Burst Type | B2 = Burst 2 |
| Die Rev | A = A |
| Read Latency (RL) | blank = 1.5 clock cycles or 2.5 clock cycles |
| ODT Option | blank = No ODT |
| Product Type | DD = DDR-II, Common I/O |
| Temperature Range | blank = Commercial (0°C to 70°C) |
| Speed | 250 = 250MHz |
| Outpack | Tape on Reel |
The 36Mb IS61DDB21M36A and IS61DDB22M18A are synchronous, high-performance CMOS static random access memory (SRAM) devices. These SRAMs have a common I/O bus. The rising edge of K clock initiates the read/write operation, and all internal operations are self-timed. Refer to the Timing Reference Diagram for Truth Table for a description of the basic operations of these DDR-II (Burst of 2) CIO SRAMs.