IS43LD32320C-25BLI

Density 1G
Org 32Mx32
Vcc 1.2/1.8V
Type LPDDR2
Refresh 4K
Status Prod
Pkg Pins BGA(134), PoP(168)
Speed Mhz 533, 400, 333
Comment Previous Rev IS43/46LD32320A
Temp. Grade I = Industrial Grade (-40°C to +85°C)
Solder Type L = SnAgCu
Generation C = C
Number Of Words 320 = 32M
Speed 25 = 400MHz
Operating Voltage Range LD = 1.2V - 1.8V LPDDR2
Bus Width 32 = x32
Package Type B = BGA
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade

IS43LD32320C-25BLI Features

  • Low-voltage Core and I/O Power Supplies VDD2 = 1.14-1.30V, VDDCA/VDDQ = 1.14-1.30V, VDD1 = 1.70-1.95V
  • High Speed Un-terminated Logic(HSUL_12) I/O Interface
  • Clock Frequency Range : 10MHz to 533MHz (data rate range : 20Mbps to 1066Mbps per I/O)
  • Four-bit Pre-fetch DDR Architecture
  • Multiplexed, double data rate, command/ad- dress inputs
  • Eight internal banks for concurrent operation
  • Bidirectional/differential data strobe per byte of data (DQS/DQS#)
  • Programmable Read/Write latencies(RL/WL) and burst lengths(4,8 or 16)
  • ZQ Calibration
  • On-chip temperature sensor to control self re- fresh rate
  • Partial
    • array self refresh(PASR)
  • Deep power-down mode(DPD)
  • Operation Temperature Commercial (TC = 0°C to 85°C) Industrial (TC = -40°C to 85°C) Automotive, A1 (TC = -40°C to 85°C) Automotive, A2 (TC = -40°C to 105°C) options

Overview

Clock: CK and CK# are differential clock inputs. All Double Data Rate (DDR) CA inputs are sampled on both positive and negative edge of CK. Single Data Rate (SDR) inputs, CS# and CKE, are sampled at the positive Clock edge. Clock is defined as the differential pair, CK and CK#. The positive Clock edge is defined by the crosspoint of a rising CK and a falling CK#. The negative Clock edge is defined by the crosspoint of a falling CK and a rising CK#. Clock Enable: CKE HIGH activates and CKE LOW deactivates internal clock signals and therefore device input buffers and output drivers. Power savings modes are entered and exited through CKE transitions. CKE is considered part of the command code. See Command Truth Table for command code descriptions. CKE is sampled at the positive Clock edge. Chip Select: CS# is considered part of the command code. See Command Truth Table for command code descriptions. CS# is sampled at the positive Clock edge. DDR Command/Address Inputs: Uni-directional command/address bus inputs. CA is considered part of the command code. See Command Truth Table for command code descriptions. Data Inputs/Output: Bi-directional data bus.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43LD32320C-25BLI-TR 691 IS46LD32320C-18BLA2-TR 43
IS43LD32320C-18BL IS46LD32320C-18BPLA1
IS43LD32320C-18BL-TR IS46LD32320C-18BPLA1-TR
IS43LD32320C-18BLI 717 9 IS46LD32320C-18BPLA2 44
IS43LD32320C-18BLI-TR 6,000 IS46LD32320C-18BPLA2-TR
IS43LD32320C-18BPLI 2,730 17 IS46LD32320C-25BLA1 5 4
IS43LD32320C-18BPLI-TR IS46LD32320C-25BLA1-TR
IS43LD32320C-25BL 5,618 147 IS46LD32320C-25BLA2 4 16
IS43LD32320C-25BL-TR IS46LD32320C-25BLA2-TR
IS43LD32320C-25BPLI IS46LD32320C-25BPLA1 2 2
IS43LD32320C-25BPLI-TR IS46LD32320C-25BPLA1-TR
IS46LD32320C-18BLA1 IS46LD32320C-25BPLA2 2 2
IS46LD32320C-18BLA1-TR IS46LD32320C-25BPLA2-TR
IS46LD32320C-18BLA2 56 12