IS43QR81024A-075VBL
Features
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Standard Voltage : VDD = VDDQ = 1.2V, VPP=2.5V
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High speed data transfer rates with system frequency
up to 3200 Mbps
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Data Integrity
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- Auto Self Refresh (ASR) by DRAM built-in TS
- Auto Refresh and Self Refresh Modes
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DRAM access bandwidth
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- Separated IO gating structures by Bank Groups
- Self Refresh Abort
- Fine Granularity Refresh
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Signal Synchronization
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- Write Leveling via MR settings
- Read Leveling via MPR
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Reliability & Error Handling
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- Command/Address Parity
- Data bus Write CRC
- MPR readout
- Boundary Scan
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Speed Grade (CL-TRCD-TRP)
/ 17-17-17 (-083T)
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- 2400Mbps
- 2666Mbps/ 19-19-19 (-075V)
- 2933Mbps / 21-21-21 (-068Y)
- 3200Mbps/ 22-22-22 (-062AA)
PROGRAMMABLE FUNCTIONS
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Output Driver Impedance (34/48)
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CAS Write Latency (9/10/11/12/14/16/18/20)
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Additive Latency (0/CL-1/CL-2)
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CS# to Command Address (3/4/5/6/8)
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Burst Type (Sequential/Interleaved)
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Write Recovery Time (10/12/14/16/18/20/24)
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Read Preamble (1T/2T)
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Write Preamble (1T/2T)
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Burst Length (BL8/BC4/BC4 or 8 on the fly)
Options
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Configuration : 512Mx16, 1Gx8
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Package:
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- 96-ball BGA (10mm x 14mm, 0.8mm ball pitch) for x16
- 78-ball BGA (10mm x 14mm, 0.8mm ball pitch) for x8
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Signal Integrity
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- Internal VREFDQ Training
- Read Preamble Training
- Gear Down Mode
- Per DRAM Adressability
- Configurable DS for system compatibility
- Configurable On-Die Termination
- Data bus Inversion (DBI)
- ZQ Calibration for DS/ODT impedance accuracy via external
ZQ pad (240 ohm +/- 1%)
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Power Saving and efficiency
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- POD with VDDQ termination
- Command/Address Latency (CAL)
- Maximum Power Saving
- Low power Auto Self Refresh (LPASR)