IS43DR81280C-3DBL-TR

Density	1G
Org	128Mx8
Vcc	1.8V
Type	DDR2
Refresh	8K
Speed	3 = 333MHz
Status	Prod
Comment
Pkg Pins	BGA(60)
Product Family	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Temp. Grade	blank = Commercial Grade (0°C to +70°C)
Solder Type	L = SnAgCu
Number Of Words	1280 = 128M
CL (CAS Latency)	D = 5
Generation	C = C
Operating Voltage Range	DR = 1.8V DDR2
Bus Width	8 = x8
Package Type	B = BGA
Outpack	Tape on Reel

Datasheet

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IS43DR81280C-3DBL-TR Features

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Double data rate interface: two data transfers per clock cycle
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
8 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, 6 and 7 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, 5 and 6 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT) OPTIONS
Configuration(s): 128Mx8 (16Mx8x8 banks): IS43/46DR81280C 64Mx16 (8Mx16x8 banks): IS43/46DR16640C
Package: x8: 60-ball BGA (8mm x 10.5mm) x16: 84-ball WBGA (8mm x 12.5mm)
Timing
- Cycle time 2.5ns @CL=5 DDR2-800D 2.5ns @CL=6 DDR2-800E 3.0ns @CL=5 DDR2-667D 3.75ns @CL=4 DDR2-533C 5ns @CL=3 DDR2-400B

Overview

ISSI's 1Gb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls.

Related Part Number(s)

Description	Available Qty	Description	Available Qty
IS43DR81280C-3DBL	5,000	IS43DR81280C-25DBLI-TR	2,000
IS43DR81280C-25DBL	1,452	IS43DR81280C-3DBLI	5,000
IS43DR81280C-25DBL-TR	4,000	IS43DR81280C-3DBLI-TR
IS43DR81280C-25DBLI	5,082