IS43DR32800A-5BBL

Org	8Mx32
Pkg(Pins)	BGA(126)
Vcc	1.8V
Refresh	8K
Speed	5 = 200MHz
No. of Words	8M
Models	IBIS
Solder	SnAgCu
Status	OBS
Comment	Reduced page option
Type	DDR2
Bus Width	32 = x32
Temp.Range	Commercial Grade (0C to +70°C)
CL (CAS Latency)	B = 3
Generation/Rev	A
Product Family	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Temp. Grade	blank = Commercial Grade (0°C to +70°C)
Solder Type	L = SnAgCu
Number Of Words	800 = 8M
Generation	A = A
Operating Voltage Range	DR = 1.8V DDR2
Package Type	B = BGA

Datasheet

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IS43DR32800A-5BBL Features

Vdd = 1.8V ±0.1V, Vddq = 1.8V ±0.1V
JEDEC standard 1.8V I/O (SSTL_18-compatible)
Differential data strobe (DQS, DQS)
4-bit prefetch architecture
On chip DLL to align DQ and DQS transitions with CK
4 internal banks for concurrent operation
Programmable CAS latency (CL) 3, 4, 5, and 6 supported
Posted CAS and programmable additive latency (AL) 0, 1, 2, 3, 4, and 5 supported
WRITE latency = READ latency - 1 tCK
Programmable burst lengths: 4 or 8
Adjustable data-output drive strength, full and reduced strength options
On-die termination (ODT) OPTIONS
Configuration: 8M x 32 (IS43DR32800A Standard Page - 4K refresh) 8M x 32 (IS43/46DR32801A Reduced Page - 8K refresh)
Package: x32: 126 WBGA
Timing
- Cycle time 3.0ns @CL=5, DDR2-667D 3.75ns @CL=4, DDR2-533C 5.0ns @CL=3, DDR2-400B

Overview

ISSI's 256Mb DDR2 SDRAM uses a double-data-rate architecture to achieve high-speed operation. The double-data rate architecture is essentially a 4n-prefetch architecture, with an interface designed to transfer two data words per clock cycle at the I/O balls. The 256Mb DDR2 SDRAM is provided in a wide bus x32 format, designed to offer a smaller footprint and support compact designs.