IS43DR16640A-3DBL

Density	1G
Org	128Mx8
Pkg(Pins)	BGA(60)
Vcc	1.8V
Refresh	8K
Speed	3 = 333MHz
No. of Words	64M
Models	IBIS
Solder	SnAgCu
Status	OBS
Type	DDR2
Bus Width	16 = x16
Temp.Range	Commercial Grade (0C to +70°C)
CL (CAS Latency)	D = 5
Generation/Rev	A
Product Family	43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Temp. Grade	blank = Commercial Grade (0°C to +70°C)
Solder Type	L = SnAgCu
Number Of Words	640 = 64M
Generation	A = A
Operating Voltage Range	DR = 1.8V DDR2
Package Type	B = BGA

Datasheet

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IS43DR16640A-3DBL Features

Clock frequency up to 400MHz
8 internal banks for concurrent operation
4‐bit prefetch architecture
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
Write Latency = Read Latency‐1
Programmable Burst Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 s (8192 cycles/64 ms)
OCD (Off‐Chip Driver Impedance Adjustment)
ODT (On‐Die Termination)
Weak Strength Data‐Output Driver Option OPTIONS
Configuration:  128Mx8 (16M x 8 x 8 banks)  64Mx16 (8M x 16 x 8 banks)
Package:  60‐ball TW‐BGA for x8  84‐ball TW‐BGA for x16 SEPTEMBER 2011
Bidirectional differential Data Strobe (Single‐ ended data‐strobe is an optional feature)
On‐Chip DLL aligns DQ and DQs transitions with CK transitions
DQS# can be disabled for single‐ended data strobe
Read Data Strobe supported (x8 only)
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported

Overview

Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect.