IS43DR16640

Density	1G
Org	64Mx16
Vcc	1.8V
Type	DDR2
Refresh	8K
Speed	800, 667, 533, 400
Status	Contact ISSI
Comment
Pkg Pins	BGA(84)

IS43DR16640 Features

Clock frequency up to 533MHz
8 internal banks for concurrent operation
4‐bit prefetch architecture
Programmable CAS Latency: 3, 4, 5, 6 and 7
Programmable Additive Latency: 0, 1, 2, 3, 4, 5 and 6
Write Latency = Read Latency‐1
Programmable Burst Sequence: Sequential or Interleave
Programmable Burst Length: 4 and 8
Automatic and Controlled Precharge Command
Power Down Mode
Auto Refresh and Self Refresh
Refresh Interval: 7.8 μs (8192 cycles/64 ms)
OCD (Off‐Chip Driver Impedance Adjustment)
ODT (On‐Die Termination)
Weak Strength Data‐Output Driver Option OPTIONS
Configuration: − 128Mx8 (16M x 8 x 8 banks) − 64Mx16 (8M x 16 x 8 banks)
Package: − 60‐ball FBGA for x8 − 84‐ball FBGA for x16 Clock Cycle Timing ‐37C PRELIMINARY INFORMATION MARCH 2010
Bidirectional differential Data Strobe (Single‐ ended data‐strobe is an optional feature)
On‐Chip DLL aligns DQ and DQs transitions with CK transitions
DQS# can be disabled for single‐ended data strobe
Read Data Strobe supported (x8 only)
Differential clock inputs CK and CK#
VDD and VDDQ = 1.8V ± 0.1V
PASR (Partial Array Self Refresh)
SSTL_18 interface
tRAS lockout supported

Overview

Input clocks Clock enable Chip Select Command control inputs Address Bank Address I/O Upper Byte Data Strobe Lower Byte Data Strobe Input data mask Supply voltage Ground DQ power supply DQ ground Reference voltage DLL power supply DLL ground On Die Termination Enable No connect.

IS43DR16640 Features

Overview

Related Part Number(s)