IS43R83200D-6TL

Density 256M
Org 32Mx8
Vcc 2.5V
Type DDR
Refresh 8K
Speed 6 = 166MHz
Status NR
Comment
Pkg Pins TSOP2(66)
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Temp. Grade blank = Commercial Grade (0°C to +70°C)
Solder Type L = 100% matte Sn
Number Of Words 3200 = 32M
Generation D = D
Operating Voltage Range R = 2.5V DDR or 2.5V SDR
Bus Width 8 = x8
Package Type T = TSOP

IS43R83200D-6TL Features

  • VDD and VDDQ: 2.5V ± 0.2V
  • SSTL_2 compatible I/O
  • Double-data rate architecture; two data transfers per clock cycle
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
  • Differential clock inputs (CK and CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Four internal banks for concurrent operation
  • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
  • Burst Length: 2, 4 and 8
  • Burst Type: Sequential and Interleave mode
  • Programmable CAS latency: 2, 2.5 and 3
  • Auto Refresh and Self Refresh Modes
  • Auto Precharge
  • TRAS Lockout supported (tRAP = tRCD) OPTIONS
  • Configuration(s): 8Mx32, 16Mx16, 32Mx8
  • Package(s): 144 Ball BGA (x32) 66-pin TSOP-II (x8, x16) and 60 Ball BGA (x8, x16)
  • Lead-free package available

Overview

ISSI’s 256-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 268,435,456-bit memory array is internally organized as four banks of 64Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 8-bit, 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43R83200D-6TL-TR 6,776 IS43R83200D-5TLI 5,000
IS43R83200D IS43R83200D-5TLI-TR
IS43R83200D-5TL 50,000 IS43R83200D-6TLI 5,000
IS43R83200D-5TL-TR 6,500 IS43R83200D-6TLI-TR 6,500