IS43R32400E-5BLI-TR

Density 128M
Org 4Mx32
Vcc 2.5V
Type DDR
Refresh 4K
Speed 5 = 200MHz
Status Prod
Comment
Pkg Pins BGA(144)
Temp. Grade I = Industrial Grade (-40°C to +85°C)
Solder Type L = SnAgCu
Generation E = E
Number Of Words 400 = 4M
Operating Voltage Range R = 2.5V DDR or 2.5V SDR
Bus Width 32 = x32
Package Type B = BGA
Product Family 43 = DDR/DDR2/DDR3/DDR4 Commercial/Industrial grade
Outpack Tape on Reel

IS43R32400E-5BLI-TR Features

  • VDD and VDDQ: 2.5V ± 0.2V (-5,-6)
  • VDD and VDDQ: 2.5V ± 0.1V (-4)
  • SSTL_2 compatible I/O
  • Double-data rate architecture; two data transfers per clock cycle
  • Bidirectional, data strobe (DQS) is transmitted/ received with data, to be used in capturing data at the receiver
  • DQS is edge-aligned with data for READs and centre-aligned with data for WRITEs
  • Differential clock inputs (CK and CK)
  • DLL aligns DQ and DQS transitions with CK transitions
  • Commands entered on each positive CK edge; data and data mask referenced to both edges of DQS
  • Four internal banks for concurrent operation
  • Data Mask for write data. DM masks write data at both rising and falling edges of data strobe
  • Burst Length: 2, 4 and 8
  • Burst Type: Sequential and Interleave mode
  • Programmable CAS latency: 2, 2.5, 3, and 4
  • Auto Refresh and Self Refresh Modes
  • Auto Precharge
  • Tras Lockout supported (trap = trcd) OPTIONS
  • Configuration(s): 4Mx32, 8Mx16
  • Package(s): 144 Ball BGA (x32) 66-pin TSOP-II (x16) and 60 Ball BGA (x16)
  • Lead-free package available

Overview

ISSI’s 128-Mbit DDR SDRAM achieves high speed data transfer using pipeline architecture and two data word accesses per clock cycle. The 134,217,728-bit memory array is internally organized as four banks of 32Mb to allow concurrent operations. The pipeline allows Read and Write burst accesses to be virtually continuous, with the option to concatenate or truncate the bursts. The programmable features of burst length, burst sequence and CAS latency enable further advantages. The device is available in 16-bit and 32-bit data word size Input data is registered on the I/O pins on both edges of Data Strobe signal(s), while output data is referenced to both edges of Data Strobe and both edges of CLK. Commands are registered on the positive edges of CLK. An Auto Refresh mode is provided, along with a Self Refresh mode. All I/Os are SSTL_2 compatible. ADDRESS TABLE Parameter 4M x 32 1M x 32 x 4 Configuration banks BA0, BA1.

 

Related Part Number(s)

Description Stock Qty Available Qty Description Stock Qty Available Qty
IS43R32400E-5BLI 5,000 IS43R32400E-6BL
IS43R32400E-4BL 257 50,000 IS43R32400E-6BL-TR
IS43R32400E-4BL-TR 6,500 IS43R32400E-6BLI
IS43R32400E-5BL 1,083 50,000 IS43R32400E-6BLI-TR
IS43R32400E-5BL-TR 6,500